A decoding system of a known magnetic recording apparatus has a construction such as the one shown in FIG.1. Therein, 11 represents a magnetic head for reproducing recorded data from a recording medium such as a magnetic disk, 12 an amplifier, 13 an equalizer, 14 a pulse shaper, 15 a phase locked loop (PLL), 16 a equalizer, 17 an A/D converter (A/D), and 18 a Viterbi decoder.
A signal reproduced by the magnetic head 11 is amplified by the amplifier 12, subjected to equalizing amplification by the equalizers 13 and 16 consisting of filters, for example, and has its noise removed. The pulse shaper 14 generates pulses by peak detection, and a clock signal is obtained by means of the phase locked loop 15, which signal is synchronous with a read-out signal. This clock signal is then used as a sampling clock signal of the A/D converter 17; the read-out signal, equalized by the equalizer 16, is furnished to the A/D converter 17 and sampled thereby, responsive to the one-bit-rate sampling clock signal from the phase locked loop 15, so as to be converted to a digital signal. Sample values of the read-out signal, thus converted to a digital signal, all furnished to the Viterbi decoder 8 so as to be decoded by maximum-likelihood decoding.
Viterbi decoder is known as a maximum-likelihood decoder for convolution codes and comprises, as shown in FIG. 2, a distributor 21, ACS circuits 22-1-22-4, a path memory 23, a normalizing circuit 24 and a path selector 25, the distributor 21 being used in computing a branch metric value for distribution to ACS circuits 22-1-22-4. Given that the constraint length of convolution codes is k, the number of ACS circuits to be provided is 2.sup.k-1. The provision of 4 ACS circuits provided in FIG. 2 indicates a case in which the constraint length k=3.
Each of the ACS circuits 22-1-22-4 comprises an adder (A), a comparator (C) and a selector (S), in which the adder (A) adds the branch metric value and the previous metric value, the comparator (C) compares those values, and the the selector (S) selects the smaller metric value as the path metric value of the survivor path. The path selection signal thereof is stored in the path memory 23. The path memory 23, containing a number of stages of path memory cells which is as many as 4-5 times that of the constraint length k, stores the signal as the survivor path. The output of the final stage is furnished to the path selector 25, after which the path corresponding to the smallest path metric value is selected. The decoded output is thus obtained. When the number of digits becomes so large as to cause an overflow in computing the path metric value, the normalizing circuit 24 normalizes the path metric value. When employing a Viterbi decoder of this configuration in decoding a signal subject to intersymbol interference, the ACS circuits create a new path metric value by adding the previous path metric value to the output obtained by squaring the difference between the assumed sample value and the actual sample value. The ACS circuits then compares each path metric value and select the smallest of the path metric values, namely the values output from the adder. The selected value becomes the next path metric value and is stored in the path memory 73.
FIG. 3 illustrates a trellis diagram obtained when the constraint length is 3, solid arrows indicating a transition when an input data is "0", broken arrows indicating a transition when an input data is "1", and circles indicating an internal state. For example, the assumed sample values on paths P0 and P1 can be assumed to be Y.sub.p0 and Y.sub.p1 indicated by solid black circles in waveforms (a) and (b) of FIG. 4. These values are obtained from 3 bits of assumed path values (a.sub.-1, a.sub.0, a.sub.1) shown in the range of "present" in FIG. 4 (a). Given that a sample value taken from an isolated waveform of FIG. 4 (C) taken at one-bit rate is g.sub.i, the constraint length k, and m=(k-1)/2, y is obtained by ##EQU1## For example, when the constraint length k=3, m=1. Therefore, Y.sub.P0 and Y.sub.P1 will be obtained by calculating (1) in the range from i=-1 to i=+1.
If we take into consideration interference from past data, values stored in the memory (b.sub.2, b.sub.3, . . . ) will be taken advantage of as follows. ##EQU2##
FIG. 5 is a block diagram of the main portion of an example of known technology in which a past data is taken into consideration and the calculation of (2) is conducted. This example comprises an ACS circuit 31, a path memory 32, a path selector 33 and an assumed path memory 34, wherein sample values of a signal, the read-out signal of magnetic disk apparatuses, for example, which signal is to be decoded, is furnished to the ACS circuit 31. Each of the path memory 32 and the assumption path memory 34 is constructed of a combination of shift registers capable of storing "1", "0" and "-1" because the read-out signal of magnetic recording apparatuses have polarity. The assumption path memory 34 stores a plurality of mutually different assumed data sequences.
Assumed sample values, allowing for interference from past data, are obtained on the basis of these assumed data sequences and the contents of the path memory 32. The ACS circuit 31 adds the output obtained by squaring a difference between the assumed sample value and the sample value of the read-out signal, for example to the previously computed path metric value. The ACS circuit then compares outputs from the adder and selects the smaller of the two values, which is designated as the next metric value. The last-in-line value of the assumed path memory 34 is furnished to the path memory 32.
Accordingly, while the value of the path memory 32 is not the most likely one as the decoded value, it is the tentatively likely one because it is in series with the assumed path memory. The path selector 33 detects the smallest tentative path metric value, selects a path leading to the status, and outputs the last-in-line data as the decoded output. Arrows connecting the path memory 22 and the assumption path memory 34 indicate conducting multiplication and addition, as directed by equation (2) and obtaining a tentative assumed sample value.
As described before, by allowing for interference from past data, an accurate assumption of assumed sample value is possible. However, when considering a path preceding by one bit (one bit before the present moment), assumed sample values when designating, as P00 and P10, the paths following the path P0 in the trellis diagram of FIG. 3, a large error is produced unless we take into account y.sub.P00 and Y.sub.P10 respectively shown as black solid circles in waveforms (d) and (e) of FIG. 4. Consequently, it is necessary to increase the constraint length k, that is, to increase the number of bits of the assumed path, in order to ascertain the measure of interference accurately. However, since the scale of the decoder circuit is proportional to 2.sup.(k-1), increasing k produces a huge scale of the circuit and therefore is difficult to achieve.
In a decoding method allowing for interference from past data like, such as the known method shown in FIG. 5, no consideration is given as to the interference caused by future data and effects thereof on the current data, as described before. Hence, there is a need for a special equalization so as to cancel such an interference totally. In terms of practicality, the need for this equalization is particularly important in a magnetic disk apparatus in which the measure of interference differs from one track to another in a magnetic recording medium.